Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a technology for changing a width of a signal and controlling a transmission of a clock signal.
Semiconductor devices and Integrated Circuits (ICs) have been continuously improved to increase not only the degree of integration but also the operation speed. Many semiconductor devices and ICs operate in synchronization with a periodic pulse signal such as a clock signal, in order to increase the operation speed and perform an internal operation effectively. Therefore, such semiconductor devices and ICs operate in response to a clock signal supplied from outside or an internal clock signal generated therein.
FIG. 1 is a circuit diagram of a conventional semiconductor device.
Referring to FIG. 1, the conventional semiconductor device includes a delay unit 11 and a logic circuit 11_2.
The delay unit 11 is configured to delay a first pulse signal PULSE_IN in response to a clock signal CLK. The logic circuit 11_2 is configured to perform an OR operation on the first pulse signal PULSE_IN and a signal P_DLY outputted from the delay unit 11, and outputs a second pulse signal PULSE_OUT. Here, the second pulse signal PULSE_OUT becomes activated at an activation time of the first pulse signal PULSE_IN, and has a longer active period than the first pulse signal PULSE_IN.
Meanwhile, the delay unit 11 may include a plurality of D flip-flops which are enabled by a clock signal CLK, and the number of the D flip-flops corresponds to a delay value for delaying the first pulse signal PULSE_IN. At this time, since the clock signal CLK continuously toggles, the clock signal CLK may continue to consume current because transistors within the D flip-flops become continuously charged and discharged. Such current consumption may occur even while no signal is inputted to the D flip-flops, as well as even in a stand-by state.
FIG. 2 is a timing diagram illustrating the internal operation of the semiconductor device shown in FIG. 1.
Referring to FIG. 2, the operation of the semiconductor device shown in FIG. 1 may be described as follows.
The first pulse signal PULSE_IN is inputted to the delay unit 11, then the delay unit 11 delays the first pulse signal PULSE_IN to output a signal P_DLY in synchronization with the clock signal CLK. Then, the logic circuit 11_2 performs an OR operation on the first pulse signal PULSE_IN and the delayed signal P_DLY, and outputs a second pulse signal PULSE_OUT which has a longer active period than the first pulse signal PULSE_IN.
At this time, the clock signal CLK continuously toggles regardless of the input of the first pulse signal PULSE_IN. Therefore, as described above, the clock signal CLK continues to consume current because the transistors within the D flip-flops which constitute the delay unit 11 are continuously charged and discharged. Such current consumption may occur even while no signal is inputted to the D flip-flops. Therefore, it may be one of the factors which increase the current consumption regardless of the internal operation.